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Low Distortion Differential ADC Driver AD8138
FEATURES Easy to Use Single-Ended-to-Differential Conversion Adjustable Output Common-Mode Voltage Externally Adjustable Gain Low Harmonic Distortion -94 dBc--Second, -114 dBc--Third @ 5 MHz into 800 Load -87 dBc--Second, -85 dBc--Third @ 20 MHz into 800 Load -3 dB Bandwidth of 320 MHz, G = +1 Fast Settling to 0.01% of 16 ns Slew Rate 1150 V/ s Fast Overdrive Recovery of 4 ns Low Input Voltage Noise of 5 nV//Hz 1 mV Typical Offset Voltage Wide Supply Range +3 V to 5 V Low Power 90 mW on 5 V 0.1 dB Gain Flatness to 40 MHz Available in 8-Lead SOIC and MSOP Packages APPLICATIONS ADC Driver Single-Ended-to-Differential Converter IF and Baseband Gain Block Differential Buffer Line Driver PRODUCT DESCRIPTION PIN CONFIGURATION
-IN VOCM 1 2 8 +IN 7 NC 6 V- 5 -OUT
V+ 3 +OUT 4
AD8138
NC = NO CONNECT
TYPICAL APPLICATION CIRCUIT
+5V 499 VIN 499 VOCM 499 + AVDD DVDD DIGITAL OUTPUTS VREF +5V
AIN AIN
AD8138
- 499
ADC
AVSS
The AD8138 is a major advancement over op amps for differential signal processing. The AD8138 can be used as a single-endedto-differential amplifier or as a differential-to-differential amplifier. The AD8138 is as easy to use as an op amp, and greatly simplifies differential signal amplification and driving. Manufactured on ADI's proprietary XFCB bipolar process, the AD8138 has a -3 dB bandwidth of 320 MHz and delivers a differential signal with the lowest harmonic distortion available in a differential amplifier. The AD8138 has a unique internal feedback feature that provides balanced output gain and phase matching, suppressing even order harmonics. The internal feedback circuit also minimizes any gain error that would be associated with the mismatches in the external gain setting resistors. The AD8138's differential output helps balance the input-todifferential ADCs, maximizing the performance of the ADC.
The AD8138 eliminates the need for a transformer with high performance ADCs, preserving the low frequency and dc information. The common-mode level of the differential output is adjustable by a voltage on the VOCM pin, easily level-shifting the input signals for driving single-supply ADCs. Fast overload recovery preserves sampling accuracy. The AD8138 distortion performance makes it an ideal ADC driver for communication systems, with distortion performance good enough to drive state-of-the-art 10-bit to 16-bit converters at high frequencies. The AD8138's high bandwidth and IP3 also make it appropriate for use as a gain block in IF and baseband signal chains. The AD8138 offset and dynamic performance make it well suited for a wide variety of signal processing and data acquisition applications. The AD8138 is available in both SOIC and MSOP packages for operation over -40C to +85C temperatures.
REV. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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(@ 25 C, VS = 5 V, VOCM = 0, G = +1, RL,dm = 500 , unless otherwise noted. Refer to Figure 1 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless otherwise noted.)
Parameter DIN to OUT Specifications VOUT = 0.5 V p-p, CF = 0 pF VOUT = 0.5 V p-p, CF = 1 pF VOUT = 0.5 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF 0.01%, VOUT = 2 V p-p, CF = 1 pF VIN = 5 V to 0 V Step, G = +2 290 320 225 30 265 1150 16 4 -94 -87 -62 -114 -85 -57 -77 37 5 2 -2.5 1 4 3.5 -0.01 6 3 1 -4.7 to +3.4 -77 7.75 95 -66 +2.5 7 MHz MHz MHz MHz V/ms ns ns dBc dBc dBc dBc dBc dBc dBc dBm nV//Hz pA//Hz mV mV/C mA mA/C MW MW pF V dB V p-p mA dB Conditions Min Typ Max Unit
AD8138-SPECIFICATIONS
DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE* Second Harmonic VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W Third Harmonic VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W IMD 20 MHz IP3 20 MHz Voltage Noise (RTI) f = 100 kHz to 40 MHz Input Current Noise f = 100 kHz to 40 MHz INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error VOCM to OUT Specifications TMIN to TMAX Variation Differential Common Mode DVOUT,dm/DVIN,cm; DVIN,cm = 1 V Maximum DVOUT; Single-Ended Output DVOUT,cm/DVOUT,dm; DVOUT,dm = 1 V VOS,dm = VOUT,dm/2; VDIN+ = VDIN- = VOCM = 0 V TMIN to TMAX Variation
-70
DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate
NPUT VOLTAGE NOISE (RTI) f = 0.1 MHz to 100 MHz
250 330
17
MHz V/ms
nV//Hz
DC PERFORMANCE Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
VOS,cm = VOUT,cm; VDIN+ = VDIN- = VOCM = 0 V DVOUT,dm/DVOCM; DVOCM = 1 V DVOUT,cm/DVOCM; DVOCM = 1 V
3.8 200 -3.5 1 0.5 -75 0.9955 1 1.4 18
+3.5
1.0045 5.5 23 -70 +85
V kW mV mA dB V/V V mA mA/C dB C
TMIN to TMAX Variation DVOUT,dm/DVS; DVS = 1 V -40
20 40 -90
*Harmonic Distortion Performance is equal or slightly worse with higher values of R L,dm. See TPCs 13 and 14 for more information. Specifications subject to change without notice.
-2-
REV. E
AD8138
C, = V, V = 2.5 = +1, R = test setup All refer single-ended input and differential output, SPECIFICATIONS (@ 25andVlabel5 descriptions. V, Gspecifications 500 to, unless otherwise noted. Refer to Figure 1 forunless otherwise noted.)
S OCM L,dm
Parameter
DIN to OUT Specifications
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Settling Time Overdrive Recovery Time NOISE/HARMONIC PERFORMANCE* Second Harmonic
VOUT = 0.5 V p-p, CF = 0 pF VOUT = 0.5 V p-p, CF = 1 pF VOUT = 0.5 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF VOUT = 2 V p-p, CF = 0 pF 0.01%, VOUT = 2 V p-p, CF = 1 pF VIN = 2.5 V to 0 V Step, G = +2 VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W VOUT = 2 V p-p, 5 MHz, RL,dm = 800 W VOUT = 2 V p-p, 20 MHz, RL,dm = 800 W VOUT = 2 V p-p, 70 MHz, RL,dm = 800 W 20 MHz 20 MHz f = 100 kHz to 40 MHz f = 100 kHz to 40 MHz VOS,dm = VOUT,dm/2; VDIN+ = VDIN- = VOCM = 0 V TMIN to TMAX Variation TMIN to TMAX Variation Differential Common Mode
280
310 225 29 265 950 16 4 -90 -79 -60 -100 -82 -53 -74 35 5 2
MHz MHz MHz MHz V/ms ns ns dBc dBc dBc dBc dBc dBc dBc dBm nV//Hz pA//Hz +2.5 7 mV mV/C mA mA/C MW MW pF V dB V p-p mA dB
Third Harmonic
IMD IP3 Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS Offset Voltage Input Bias Current Input Resistance Input Capacitance Input Common-Mode Voltage CMRR OUTPUT CHARACTERISTICS Output Voltage Swing Output Current Output Balance Error VOCM to OUT Specifications
-2.5
VOUT,dm/ VIN,cm; VIN,cm = 1 V Maximum VOUT; Single-Ended Output VOUT,cm/ VOUT,dm; VOUT,dm = 1 V
1 4 3.5 -0.01 6 3 1 0.3 to 3.2 -77 2.9 95 -65
-70
DYNAMIC PERFORMANCE -3 dB Bandwidth Slew Rate INPUT VOLTAGE NOISE (RTI) DC PERFORMANCE Input Voltage Range Input Resistance Input Offset Voltage Input Bias Current VOCM CMRR Gain POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
Specifications subject to change without notice.
220 250 f = 0.1 MHz to 100 MHz 17 1.0 to 3.8 100 -5 1 0.5 -70 0.9968 1 2.7 15 TMIN to TMAX Variation VOUT,dm/ VS; VS = 1 V -40
MHz V/ms nV//Hz V kW mV mA dB V/V V mA mA/C dB C
VOS,cm = VOUT,cm; VDIN+ = VDIN- = VOCM = 0 V VOUT,dm/ VOCM; VOCM = 2.5 1 V VOUT,cm/ VOCM; VOCM = 2.5 1 V
+5
1.0032 11 21 -70 +85
20 40 -90
*Harmonic Distortion Performance is equal or slightly worse with higher values of R L,dm. See TPCs 13 and 14 for more information.
REV. E
-3-
AD8138
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V VOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 550 mW 2 JA (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155C/W Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. 2 Thermal resistance measured on SEMI standard four-layer board.
ABSOLUTE MAXIMUM RATINGS 1
PIN CONFIGURATION
-IN VOCM
1 2
8 +IN 7 NC 6 V- 5 -OUT
V+ 3 +OUT 4
AD8138
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function 1 -IN VOCM Negative Input Summing Node Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example, 1 V dc on VOCM will set the dc bias level on +OUT and -OUT to 1 V. Positive Supply Voltage Positive Output. Note that the voltage at -DIN is inverted at +OUT. (See Figure 2.) Negative Output. Note that the voltage at +DIN is inverted at -OUT. (See Figure 2.) Negative Supply Voltage No Connect Positive Input Summing Node 2
RF = 499 RG = 499 49.9 RG = 499 24.9
AD8138
RF = 499
RL,dm = 499
3 4 5
V+ +OUT -OUT
Figure 1. Basic Test Circuit
6 7 8
V- NC +IN
ORDERING GUIDE
Model AD8138AR AD8138AR-REEL AD8138AR-REEL7 AD8138ARM AD8138ARM-REEL AD8138ARM-REEL7 AD8138-EVAL
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 8-Lead SOIC 8-Lead SOIC 8-Lead SOIC 8-Lead MSOP 8-Lead MSOP 8-Lead MSOP Evaluation Board
Package Option R-8 13" Tape and Reel 7" Tape and Reel RM-8 13" Tape and Reel 7" Tape and Reel
Branding Information
HBA HBA HBA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8138 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-4-
REV. E
Typical Performance Characteristics-AD8138
Unless otherwise noted, Gain = 1, RG = RF = RL,dm = 499 V, TA = 25 C; refer to Figure 1 for test setup.
6 VIN = 0.2V p-p CF = 0pF 3 VS = +5V
GAIN - dB GAIN - dB
6 VS = 5V VIN = 0.2V p-p 3 CF = 0pF 0 CF = 1pF
0.5 VS = 5V VIN = 0.2V p-p 0.3 CF = 0pF
0 VS = -3 5V
GAIN - dB
0.1
-3
-0.1 CF = 1pF
-6
-6
-0.3
-9 1 10 100 FREQUENCY - MHz 1000
-9 1 10 100 FREQUENCY - MHz 1000
-0.5 1 10 FREQUENCY - MHz 100
TPC 1. Small Signal Frequency Response
TPC 2. Small Signal Frequency Response
TPC 3. 0.1 dB Flatness vs. Frequency
6 VIN = 2V p-p CF = 0pF 3 VS = +5V
GAIN - dB GAIN - dB
6 VIN = 2V p-p VS = 5V 3 CF = 0pF 0 CF = 1pF
GAIN - dB
30
20
G = 10, RF = 4.99k G = 5, RF = 2.49k
VS = 5V CF = 0pF VOUT,dm = 0.2V p-p RG = 499
0 VS = -3 5V
10 G = 2, RF = 1k G = 1, RF = 499
-3
0 -6 -6
-9 1 10 100 FREQUENCY - MHz 1000
-9 1 10 100 FREQUENCY - MHz 1000
-10 1 10 100 FREQUENCY - MHz 1000
TPC 4. Large Signal Frequency Response
TPC 5. Large Signal Frequency Response
TPC 6. Small Signal Frequency Response for Various Gains
-50 -60
DISTORTION - dBc
VOUT,dm = 2V p-p RL = 800
-40 -50
DISTORTION - dBc
-30
VOUT,dm = 4V p-p RL = 800 HD3(VS = +5V)
-40
DISTORTION - dBc
VOUT,dm = 2V p-p RL = 800 FO = 20MHz HD2(VS = +5)
-70 -80 -90 -100 -110 -120 0
-60 -70 -80
HD2(VS = +5V) HD2(VS = 5V)
-50 -60 -70 -80 -90 -100 -4 HD3(VS = +5)
HD2(VS = +5V) HD2(VS = 5V)
HD3(VS = +5V) HD3(VS = 5V)
-90 -100 -110
HD3(VS = HD2(VS = -3
5) 5)
HD3(VS = 0
5V) 70
10 20 30 40 50 60 FUNDAMENTAL FREQUENCY - MHz
70
10 20 30 40 50 60 FUNDAMENTAL FREQUENCY - MHz
-2 -1 0 1 2 VOCM DC OUTPUT - V
3
4
TPC 7. Harmonic Distortion vs. Frequency
TPC 8. Harmonic Distortion vs. Frequency
TPC 9. Harmonic Distortion vs. VOCM
REV. E
-5-
AD8138
-60 VS = 5V RL = 800 HD3(F = 20MHz) -60 VS = 5V RL = 800 HD2(F = 20MHz)
-70 -60 VS = 3V RL = 800 HD3(F = 20MHz) HD2(F = 20MHz) -80
-70
DISTORTION - dBc
-70
HD2(F = 20MHz) -80 -90 HD2(F = 5MHz) -100 HD3(F = 5MHz) -110 -120 -110 -120
DISTORTION - dBc
-80 -90
HD3(F = 20MHz)
HD2(F = 5MHz) -100 HD3(F = 5MHz)
DISTORTION - dBc
-90 HD2(F = 5MHz) -100
HD3(F = 5MHz)
0
1
2
3
4
5
6
0
1
2
3
4
-110 0.25
0.50
0.75
1.00
1.25
1.50
1.75
DIFFERENTIAL OUTPUT VOLTAGE - V p-p
DIFFERENTIAL OUTPUT VOLTAGE - V p-p
DIFFERENTIAL OUTPUT VOLTAGE - V p-p
TPC 10. Harmonic Distortion vs. Differential Output Voltage
TPC 11. Harmonic Distortion vs. Differential Output Voltage
TPC 12. Harmonic Distortion vs. Differential Output Voltage
-60 VS = 5V VOUT,dm = 2V p-p -70 HD2(F = 20MHz) -80 HD3(F = 20MHz) -90 HD2(F = 5MHz) -100 HD3(F = 5MHz) -110 200
-60 -70
VS = 5V VOUT,dm = 2V p-p HD2(F = 20MHz)
10
FC = 50MHz VS = 5V
-10
DISTORTION - dBc
DISTORTION - dBc
-80 -90
HD3(F = 20MHz)
POUT - dBm
-30 -50
HD2(F = 5MHz) -100 HD3(F = 5MHz) -110 -120 200
-70
-90 -110 49.5
600
1000 RLOAD -
1400
1800
600
1000 1400 RLOAD -
1800
49.7
49.9 50.1 50.3 FREQUENCY - MHz
50.5
TPC 13. Harmonic Distortion vs. RLOAD
TPC 14. Harmonic Distortion vs. RLOAD
TPC 15. Intermodulation Distortion
45 RL = 800
VS =
5V CF = 0pF
VOUT,dm = 0.2V p-p VS = 5V
VOUT,dm
40
INTERCEPT - dBm
VOUT-
CF = 1pF
VS = 35
5V
VOUT+
VS = +5V 30
V+DIN
25 0 20 40 60 80 FREQUENCY - MHz
1V
5ns
40mV
5ns
TPC 16. Third Order Intercept vs. Frequency
TPC 17. Large Signal Transient Response
TPC 18. Small Signal Transient Response
-6-
REV. E
AD8138
VS = 5V VOUT,dm = 2V p-p CF = 0pF CF = 0pF VOUT,dm = 2V p-p VS = 5V 200 V VS = 5V CF = 1pF VOUT,dm VS = +5V
CF = 1pF
V+DIN 400mV 400mV 1V
5ns
5ns
4ns
TPC 19. Large Signal Transient Response
TPC 20. Large Signal Transient Response
TPC 21. Settling Time
VS = 5V CF = 0pF VOUT,dm
499
CL = 10pF
CL = 5pF CL = 20pF
499 49.9 499 24.9 24.9
VS = 5V F = 20MHz V+DIN = 8V p-p G = 3(RF = 1500)
AD8138
499
24.9
CL
453
V+DIN
4V
30ns
400mV
2.5ns
TPC 22. Output Overdrive
TPC 23. Test Circuit for Cap Load Drive
TPC 24. Large Signal Transient Response for Various Cap Loads
-20 -30 VS = 5V VOUT,dm/ VIN,cm
-20 VIN = 2V p-p
499 499 49.9 499 249
BALANCE ERROR - dB
-30
-40
CMRR - dB
AD8138
499
-40 VS = -50 5V
249
-50
24.9
-60
-70 -80 1 10 100 FREQUENCY - MHz 1k
-60 VS = +5V -70 1 10 100 FREQUENCY - MHz 1k
TPC 25. CMRR vs. Frequency
TPC 26. Test Circuit for Output Balance
TPC 27. Output Balance Error vs. Frequency
REV. E
-7-
AD8138
-10 VOUT,dm/ VS -20 -30
PSRR - dB 100 SINGLE-ENDED OUTPUT
5.0
DIFFERENTIAL OUTPUT OFFSET - mV
-PSRR (VS = 5V)
IMPEDANCE -
2.5 VS = 0 5V VS = +5V
-40 -50 -60 -70 -80 -90 1 10 100 FREQUENCY - MHz 1k +PSRR (VS = +5V, 0V AND 5V)
10 VS = +5
1
VS = +3V -2.5
VS = 0.1 1 10 FREQUENCY - MHz
5V
100
-5.0 -40
-20
40 0 20 60 TEMPERATURE - C
80
100
TPC 28. PSRR vs. Frequency
TPC 29. Output Impedance vs. Frequency
TPC 30. Output Referred Differential Offset Voltage vs. Temperature
5
30
6 VS = +5V VS = 5V
A
4 VS = 3 VS = +3V 2 5V, +5V
SUPPLY CURRENT - mA
25 VS = 20 VS = +5V VS = +3V 10 5V
3
BIAS CURRENT -
GAIN - dB
80 100
0
15
-3
-6
1 -40
-20
40 0 20 60 TEMPERATURE - C
80
100
5 -40
-20
40 0 20 60 TEMPERATURE - C
-9 1 10 100 FREQUENCY - MHz 1k
TPC 31. Input Bias Current vs. Temperature
TPC 32. Supply Current vs. Temperature
TPC 33. VOCM Frequency Response
100
1000
VOUT,cm
INPUT CURRENT NOISE - pA/ Hz
INPUT VOLTAGE NOISE - nV/ Hz
VS = 5V VOCM = -1V TO +1V
100
10
5.7nV/ Hz
10
1.1pA / Hz
400mV
5ns
1 10
100
1k 10k 100k FREQUENCY - Hz
1M
1 10
100
1k 10k 100k FREQUENCY - Hz
1M
TPC 34. VOCM Transient Response
TPC 35. Current Noise (RTI)
TPC 36. Voltage Noise (RTI)
-8-
REV. E
AD8138
OPERATIONAL DESCRIPTION Definition of Terms
CF RF RG +IN -OUT
circuit. Excellent performance over a wide frequency range has proven difficult with this approach. The AD8138 uses two feedback loops to separately control the differential and common-mode output voltages. The differential feedback, set with external resistors, controls only the differential output voltage. The common-mode feedback controls only the common-mode output voltage. This architecture makes it easy to arbitrarily set the output common-mode level. It is forced, by internal common-mode feedback, to be equal to the voltage applied to the VOCM input, without affecting the differential output voltage. The AD8138 architecture results in outputs that are very highly balanced over a wide frequency range without requiring tightly matched external components. The common-mode feedback loop forces the signal component of the output common-mode voltage to be zeroed. The result is nearly perfectly balanced differential outputs of identical amplitude and exactly 180 apart in phase.
Analyzing an Application Circuit
+DIN VOCM -DIN
AD8138
RG -IN RF CF +OUT
RL,dm
VOUT,dm
Figure 2. Circuit Definitions
Differential voltage refers to the difference between two node voltages. For example, the output differential voltage (or equivalently output differential-mode voltage) is defined as: VOUT,dm = ( +OUT - V-OUT ) V V+OUT and V-OUT refer to the voltages at the +OUT and -OUT terminals with respect to a common reference. Common-mode voltage refers to the average of two node voltages. The output common-mode voltage is defined as: VOUT, cm = (V+OUT + V-OUT ) 2 Balance is a measure of how well differential signals are matched in amplitude and exactly 180 apart in phase. Balance is most easily determined by placing a well-matched resistor divider between the differential voltage nodes and comparing the magnitude of the signal at the divider's midpoint with the magnitude of the differential signal (see TPC 26). By this definition, output balance is the magnitude of the output common-mode voltage divided by the magnitude of the output differential-mode voltage:
Output Balance Error =
THEORY OF OPERATION
The AD8138 uses high open-loop gain and negative feedback to force its differential and common-mode output voltages in such a way as to minimize the differential and common-mode error voltages. The differential error voltage is defined as the voltage between the differential inputs labeled +IN and -IN in Figure 2. For most purposes, this voltage can be assumed to be zero. Similarly, the difference between the actual output common-mode voltage and the voltage applied to VOCM can also be assumed to be zero. Starting from these two assumptions, any application circuit can be analyzed.
Setting the Closed-Loop Gain
Neglecting the capacitors CF, the differential-mode gain of the circuit in Figure 2 can be determined to be described by the following equation: VOUT ,dm VIN ,dm = RF S RG S
VOUT , cm VOUT , dm
The AD8138 differs from conventional op amps in that it has two outputs whose voltages move in opposite directions. Like an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The AD8138 behaves much like a standard voltage feedback op amp and makes it easy to perform single-ended-to-differential conversion, commonmode level-shifting, and amplification of differential signals. Also like an op amp, the AD8138 has high input impedance and low output impedance. Previous differential drivers, both discrete and integrated designs, have been based on using two independent amplifiers and two independent feedback loops, one to control each of the outputs. When these circuits are driven from a single-ended source, the resulting outputs are typically not well balanced. Achieving a balanced output has typically required exceptional matching of the amplifiers and feedback networks. DC common-mode level-shifting has also been difficult with previous differential drivers. Level-shifting has required the use of a third amplifier and feedback loop to control the output common-mode level. Sometimes the third amplifier has also been used to attempt to correct an inherently unbalanced REV. E -9-
This assumes the input resistors, RGS, and feedback resistors, RFS, on each side are equal.
Estimating the Output Noise Voltage
Similar to the case of a conventional op amp, the differential output errors (noise and offset voltages) can be estimated by multiplying the input referred terms, at +IN and -IN, by the circuit noise gain. The noise gain is defined as:
ER GN = 1 + A F E RG
To compute the total output referred noise for the circuit of Figure 2, consideration must also be given to the contribution of the resistors RF and RG. Refer to Table I for estimated output noise voltage densities at various closed-loop gains.
Table I.
R G RF Gain ( ) ( ) 1 2 5 10 499 499 499 499 499 1.0 k 2.49 k 4.99 k
Bandwidth Output Noise Output Noise -3 dB 8138 Only 8138 + RG, RF 320 MHz 180 MHz 70 MHz 30 MHz 10 nV//Hz 15 nV//Hz 30 nV//Hz 55 nV//Hz 11.6 nV//Hz 18.2 nV//Hz 37.9 nV//Hz 70.8 nV//Hz
AD8138
When using the AD8138 in gain configurations where RF RG of one feedback network is unequal to RF RG of the other network, there will be a differential output noise due to input-referred voltage in the VOCM circuitry. The output noise is defined in terms of the following feedback terms (refer to Figure 2): b1 = for -OUT to +IN loop, and RG b2 = RF + RG for +OUT to -IN loop. With these defined, RG RF + RG RIN ,dm In the case of a single-ended input signal (for example if -DIN is grounded and the input signal is applied to +DIN), the input impedance becomes: E A RG =A RF A1 A 2 (RG + RF ) E
The circuit's input impedance is effectively higher than it would be for a conventional op amp connected as an inverter because a fraction of the differential output voltage appears at the inputs as a common-mode signal, partially bootstrapping the voltage across the input resistor RG.
Input Common-Mode Voltage Range in Single-Supply Applications
The AD8138 is optimized for level-shifting "ground" referenced input signals. For a single-ended input, this would imply, for example, that the voltage at -DIN in Figure 2 would be 0 V when the amplifier's negative power supply voltage (at V-) is also set to 0 V.
Setting the Output Common-Mode Voltage
E b - b2 VnOUT ,dm = 2VnIN ,VOCM I 1 I b1 + b2
where VnOUT,dm is the output differential noise and VnIN,VOCM is the input-referred voltage noise in VOCM.
The Impact of Mismatches in the Feedback Networks
The AD8138's VOCM pin is internally biased at a voltage approximately equal to the midsupply point (average value of the voltages on V+ and V-). Relying on this internal bias will result in an output common-mode voltage that is within about 100 mV of the expected value. In cases where more accurate control of the output common-mode level is required, it is recommended that an external source, or resistor divider (made up of 10 kW resistors), be used. The output common-mode offset listed in the Specifications section assumes the VOCM input is driven by a low impedance voltage source.
Driving a Capacitive Load
As mentioned previously, even if the external feedback networks (RF/RG) are mismatched, the internal common-mode feedback loop will still force the outputs to remain balanced. The amplitudes of the signals at each output will remain equal and 180 out of phase. The input-to-output differential-mode gain will vary proportionately to the feedback mismatch, but the output balance will be unaffected. Ratio matching errors in the external resistors will result in a degradation of the circuit's ability to reject input common-mode signals, much the same as for a four-resistor difference amplifier made from a conventional op amp. Also, if the dc levels of the input and output common-mode voltages are different, matching errors will result in a small differential-mode output offset voltage. For the G = 1 case, with a ground referenced input signal and the output common-mode level set for 2.5 V, an output offset of as much as 25 mV (1% of the difference in common-mode levels) can result if 1% tolerance resistors are used. Resistors of 1% tolerance will result in a worstcase input CMRR of about 40 dB, worst-case differential mode output offset of 25 mV due to 2.5 V level-shift, and no significant degradation in output balance error.
Calculating an Application Circuit's Input Impedance
A purely capacitive load can react with the pin and bondwire inductance of the AD8138, resulting in high frequency ringing in the pulse response. One way to minimize this effect is to place a small capacitor across each of the feedback resistors. The added capacitance should be small to avoid destabilizing the amplifier. An alternative technique is to place a small resistor in series with the amplifier's outputs as shown in TPC 23.
LAYOUT, GROUNDING, AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB environment in which it has to operate. Realizing its superior specifications requires attention to various details of good high speed PCB design. The first requirement is for a good solid ground plane that covers as much of the board area around the AD8138 as possible. The only exception to this is that the two input pins (Pins 1 and 8) should be kept a few millimeters from the ground plane, and ground should be removed from inner layers and the opposite side of the board under the input pins. This will minimize the stray capacitance on these nodes and help preserve the gain flatness versus frequency.
The effective input impedance of a circuit such as the one in Figure 2, at +DIN and -DIN, will depend on whether the amplifier is being driven by a single-ended or differential signal source. For balanced differential input signals, the input impedance (RIN,dm) between the inputs (+DIN and -DIN) is simply:
RIN,dm = 2 RG
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REV. E
AD8138
The power supply pins should be bypassed as close as possible to the device to the nearby ground plane. Good high frequency ceramic chip capacitors should be used. This bypassing should be done with a capacitance value of 0.01 mF to 0.1 mF for each supply. Further away, low frequency bypassing should be provided with 10 mF tantalum capacitors from each supply to ground. The signal routing should be short and direct to avoid parasitic effects. Wherever there are complementary signals, a symmetrical layout should be provided to the extent possible to maximize the balance performance. When running differential signals over a long distance, the traces on the PCB should be close together or any differential wiring should be twisted together to minimize the area of the loop that is formed. This will reduce the radiated energy and make the circuit less susceptible to interference.
BALANCED TRANSFORMER DRIVER
shows the differentially driven balance response. The 100 MHz balance is 35 dB better when using the AD8138. The well-balanced outputs of the AD8138 will provide a drive signal to each of the transformer's primary inputs that are of equal amplitude and 180 out of phase. Thus, depending on how the polarity of the secondary is connected, the signals that conduct across the interwinding capacitance will either both assist the transformer's secondary signal equally, or both buck the secondary signals. In either case, the parasitic effect will be symmetrical and provide a well balanced transformer output (see Figure 5).
SIGNAL WILL BE COUPLED ON THIS SIDE VIA CSTRAY CSTRAY VUNBAL 52.3 PRIMARY 500 0.005% SECONDARY VDIFF 500 0.005%
Transformers are among the oldest devices used to perform a single-ended-to-differential conversion (and vice versa). Transformers also can perform the additional functions of galvanic isolation, step-up or step-down of voltages, and impedance transformation. For these reasons, transformers will always find uses in certain applications. However, when driving a transformer single-endedly and then looking at its output, there is a fundamental imbalance due to the parasitics inherent in the transformer. The primary (or driven) side of the transformer has one side at dc potential (usually ground), while the other side is driven. This can cause problems in systems that require good balance of the transformer's differential output signals. If the interwinding capacitance (CSTRAY) is assumed to be uniformly distributed, a signal from the driving source will couple to the secondary output terminal that is closest to the primary's driven side. On the other hand, no signal will be coupled to the opposite terminal of the secondary because its nearest primary terminal is not driven (see Figure 3). The exact amount of this imbalance will depend on the particular parasitics of the transformer, but will mostly be a problem at higher frequencies. The balance of a differential circuit can be measured by connecting an equal-valued resistive voltage divider across the differential outputs and then measuring the center point of the circuit with respect to ground. Since the two differential outputs are supposed to be of equal amplitude, but 180 opposite phase, there should be no signal present for perfectly balanced outputs. The circuit in Figure 3 shows a Minicircuits T1-6T transformer connected with its primary driven single-endedly and the secondary connected with a precision voltage divider across its terminals. The voltage divider is made up of two 500 W, 0.005% precision resistors. The voltage VUNBAL, which is also equal to the ac common-mode voltage, is a measure of how closely the outputs are balanced. The plots in Figure 5 compare the transformer being driven single-endedly by a signal generator and being driven differentially using an AD8138. The top signal trace of Figure 5 shows the balance of the single-ended configuration, while the bottom
CSTRAY NO SIGNAL IS COUPLED ON THIS SIDE
Figure 3. Transformer Single-Ended-to-Differential Converter Is Inherently Imbalanced
499 CSTRAY 49.9 499 +IN OUT- VUNBAL 500 0.005% VDIFF 500 0.005% CSTRAY
499 -IN
AD8138
OUT+ 49.9 499
Figure 4. AD8138 Forms a Balanced Transformer Driver
0
OUTPUT BALANCE ERROR - dB
-20
-40
VUNBAL, FOR TRANSFORMER WITH SINGLE-ENDED DRIVE
-60
-80 VUNBAL, DIFFERENTIAL DRIVE
-100 0.3
1
10 FREQUENCY - MHz
100
500
Figure 5. Output Balance Error for Circuits of Figures 3 and 4
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AD8138
HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 6 shows a simplified front-end connection for an AD8138 driving an AD9224, a 12-bit, 40 MSPS A/D converter. The ADC works best when driven differentially, which minimizes its distortion as described in its data sheet. The AD8138 eliminates the need for a transformer to drive the ADC and performs single-ended-to-differential conversion, common-mode level-shifting, and buffering of the driving signal. The positive and negative outputs of the AD8138 are connected to the respective differential inputs of the AD9224 via a pair of 49.9 W resistors to minimize the effects of the switched-capacitor front end of the AD9224. For best distortion performance, it is run from supplies of 5 V. The AD8138 is configured with unity gain for a single-ended input-to-differential output. The additional 23 W, 523 W total, at the input to -IN is to balance the parallel impedance of the 50 W source and its 50 W termination that drives the noninverting input.
The signal generator has a ground-referenced, bipolar output, i.e., it drives symmetrically above and below ground. Connecting VOCM to the CML pin of the AD9224 sets the output commonmode of the AD8138 at 2.5 V, which is the midsupply level for the AD9224. This voltage is bypassed by a 0.1 mF capacitor. The full-scale analog input range of the AD9224 is set to 4 V p-p, by shorting the SENSE terminal to AVSS. This has been determined to be the scaling to provide minimum harmonic distortion. For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p while providing signals that are 180 out of phase. With a common-mode voltage at the output of 2.5 V, this means that each AD8138 output will swing between 1.5 V and 3.5 V. A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used to test the circuit in Figure 6. When the combined-device circuit was run with a sampling rate of 20 MSPS, the SFDR (spuriousfree dynamic range) was measured at -85 dBc.
+5V
+5V
499
0.1pF
0.1pF
499
50 SOURCE
+
VOCM
49.9
VINB
AVDD DRVDD
49.9
523
AD8138
AD9224
49.9
DIGITAL OUTPUTS
VINA AVSS
SENSE CML
DRVSS
0.1pF
499
-5V
Figure 6. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS A/D Converter
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AD8138
3 V OPERATION
The circuit in Figure 7 shows a simplified front end connection for an AD8138 driving an AD9203, a 10-bit, 40 MSPS A/D converter that is specified to work on a single 3 V supply. The ADC works best when driven differentially to make the best use of the signal swing available within the 3 V supply. The appropriate outputs of the AD8138 are connected to the appropriate differential inputs of the AD9203 via a low-pass filter. The AD8138 is configured for unity gain for a single-ended input to differential output. The additional 23 W at the input to -IN is to balance the impedance of the 50 W source and its 50 W termination that drives the noninverting input. The signal generator has ground-referenced, bipolar output, i.e., it can drive symmetrically above and below ground. Even though the AD8138 has ground as its negative supply, it can still function as a level-shifter with such an input signal. The output common mode is raised up to midsupply by the voltage divider that biases VOCM. In this way, the AD8138 provides dc coupling and level-shifting of a bipolar signal, without inverting the input signal. The low-pass filter between the AD8138 and the AD9203 provides filtering that helps to improve the signal-to-noise ratio. Lower noise can be realized by lowering the pole frequency, but the bandwidth of the circuit will be lowered.
+3V 499 0.1 F 10k 499 49.9 523 0.1 F 499 10k 0.1 F +3V
The circuit was tested with a -0.5 dBFS signal at various frequencies. Figure 8 shows a plot of the total harmonic distortion (THD) vs. frequency at signal amplitudes of 1 V and 2 V differential drive levels.
-40 -45 -50 -55 AD8138-2V -60 -65 AD8138-1V -70 -75 -80 0 5 10 15 FREQUENCY - MHz 20 25
THD - dBc SINAD - dBc
Figure 8. AD9203 THD @ -0.5 dBFS AD8138
Figure 9 shows the signal to noise plus distortion (SINAD) under the same conditions as above. For the smaller signal swing, the AD8138 performance is quite good, but its performance degrades when trying to swing too close to the supply rails.
65
0.1 F
63 61
+
49.9 20pF 49.9 20pF
AVDD AINN AINP
DRVDD DIGITAL OUTPUTS
59 57 55 53 51 49 AD8138-2V AD8138-1V
AD8138
AD9203
AVSS DRVSS
Figure 7. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter
47 45 0 5 10 15 FREQUENCY - MHz 20 25
Figure 9. AD9203 SINAD @ -0.5 dBFS AD8138
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AD8138
OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] (R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968) 4.80 (0.1890)
8 5 4
4.00 (0.1574) 3.80 (0.1497)
1
6.20 (0.2440) 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE
1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075)
0.50 (0.0196) 0.25 (0.0099)
45
0.51 (0.0201) 0.33 (0.0130)
1.27 (0.0500) 0.41 (0.0160)
COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
8-Lead Mini Small Outline Package [MSOP] (RM-8)
Dimensions shown in millimeters
3.00 BSC
8
5
3.00 BSC
1 4
4.90 BSC
PIN 1 0.65 BSC 0.15 0.00 0.38 0.22 COPLANARITY 0.10 1.10 MAX 8 0 0.80 0.40
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
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AD8138 Revision History
Location 3/03--Data Sheet changed from REV. D to REV. E. Page
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Changes to TPC 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Added new paragraph after Table I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7/02--Data Sheet changed from REV. C to REV. D.
Addition of TPC 35 and TPC 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6/01--Data Sheet changed from REV. B to REV. C.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
REV. E
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C01073-0-3/03(E)

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